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(R)
L5991 L5991A
PRIMARY CONTROLLER WITH STANDBY
CURRENT-MODE CONTROL PWM SWITCHING FREQUENCY UP TO 1MHz LOW START-UP CURRENT (< 120A) HIGH-CURRENT OUTPUT DRIVE SUITABLE FOR POWER MOSFET (1A) FULLY LATCHED PWM LOGIC WITH DOUBLE PULSE SUPPRESSION PROGRAMMABLE DUTY CYCLE 100% AND 50% MAXIMUM DUTY CYCLE LIMIT STANDBY FUNCTION PROGRAMMABLE SOFT START PRIMARY OVERCURRENT FAULT DETECTION WITH RE-START DELAY PWM UVLO WITH HYSTERESIS IN/OUT SYNCHRONIZATION LATCHED DISABLE INTERNAL 100ns LEADING EDGE BLANKING OF CURRENT SENSE PACKAGE: DIP16 AND SO16 DESCRIPTION This primary controller I.C., developed in BCD60II technology, has been designed to implement off BLOCK DIAGRAM
SYNC 1 RCT 2 TIMING 25V DC-LIM 15
MULTIPOWER BCD TECHNOLOGY
DIP16
SO16
ORDERING NUMBERS: L5991/L5991A (DIP16) L5991D/L5991AD (SO16)
line or DC-DC power supply applications using a fixed frequency current mode control. Based on a standard current mode PWM controller this device includes some features such as programmable soft start, IN/OUT synchronization, disable (to be used for over voltage protection and for power management), precise maximum Duty Cycle Control, 100ns leading edge blanking on current sense, pulse by pulse current limit, overcurrent protection with soft start intervention, and Standby function for oscillator frequency reduction when the converter is lightly loaded.
VCC 8
VREF 4
DC
3
+ T DIS
Vref +
15V/10V
-
PWM UVLO 9 VC
DIS
2.5V 13V BLANKING S R
PWM
OVER CURRENT ISEN 13 + FAULT SOFT-START
SS
1.2V 7
August 2001
+ 10 OUT Q
VREF OK CLK DIS
-
14
VREF
11 16
PGND ST-BY
STAND-BY +
E/A
2.5V
2R 1V R 12 SGND 6 COMP
-
5
VFB
D97IN725A
1/23
L5991 - L5991A
ABSOLUTE MAXIMUM RATINGS
Symbol VCC IOUT Parameter Supply Voltage (ICC < 50mA) (*) Output Peak Pulse Current Analog Inputs & Outputs (6,7) Analog Inputs & Outputs (1,2,3,4,5,15,14, 13, 16) Power Dissipation @ Tamb = 70C (DIP16) @ Tamb = 50C (SO16) Junction Temperature, Operating Range Storage Temperature, Operating Range Value selflimit 1.5 -0.3 to 8 -0.3 to 6 1 0.83 -40 to 150 -55 to 150 Unit V A V V W W C C
Ptot Tj Tstg
(*) maximum package power dissipation limits must be observed
PIN CONNECTION
SYNC RCT DC VREF VFB COMP SS VCC 1 2 3 4 5 6 7 8 16 15 14 13 12 11 10 9 ST-BY DC-LIM DIS ISEN SGND PGND OUT VC
THERMAL DATA
Symbol Rth j-amb Parameter Thermal Resistance Junction -Ambient (DIP16) Thermal Resistance Junction -Ambient (SO16) Value 80 120 Unit C/W C/W
PIN FUNCTIONS
N. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Name SYNC RCT DC VREF VFB COMP SS VCC VC OUT PGND SGND ISEN DIS DC-LIM ST-BY Function Synchronization. A synchronization pulse terminates the PWM cycle and discharges Ct Oscillator pin for external CT, RA, RB components Duty Cycle control 5.0V +/-1.5% reference voltage @ 25C Error Amplifier Inverting input Error Amplifier Output Soft start pin for external capacitor Css Supply for internal "Signal" circuitry Supply for Power section High current totem pole output Power ground Signal ground Current sense Disable. It must never be left floating. TIE to SGND if not used. Connecting this pin to Vref, DC is limited to 50%. If it is left floating or grounded no limitation is imposed Standby. Connect a resistor to RCT. Connect to VREF or floating if not used.
2/23
L5991 - L5991A
ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105C; RT = 13.3k (*) CT = 1nF; unless otherwise specified.)
Symbol Parameter REFERENCE SECTION VREF Output Voltage Line Regulation Load Regulation TS Temperature Stability Total Variation Short Circuit Current IOS Power Down/UVLO OSCILLATOR SECTION Initial Accuracy Test Condition Tj = 25C; IO = 1mA VCC = 12 to 20V; T j = 25C IO = 1 to 10mA; Tj = 25C Line, Load, Temperature Vref = 0V VCC = 6V; Isink = 0.5mA pin 15 = Vref; Tj = 25C; Vcomp = 4.5V pin 15 = Vref; VCC = 12 to 20V Vcomp = 4.5V pin 15 = Vref; VCC = 12 to 20V Vcomp = 2V pin 3 = 0,7V, pin 15 = VREF pin 3 = 0.7V, pin 15 = OPEN pin 3 = 3.2V, pin 15 = VREF pin 3 = 3.2V, pin 15 = OPEN pin 3 = 2.79V, pin 15 = OPEN Min. 4.925 Typ. 5.0 2.0 2.0 0.4 5.0 0.2 95 93 46.5 100 100 50 Max. 5.075 10 10 5.130 150 0.5 105 107 53.5 0 0 47 93 75 2.8 0.75 Unit V mV mV mV/C V mA V kHz kHz kHz % % % % % V V A V dB dB V V mA mA MHz V/s A V ns V/V V A A V V ns 1.0 10 9 10.5 10 13 2 V V V V A
4.80 30
Duty Cycle
Duty Cycle Accuracy Oscillator Ramp Peak Oscillator Ramp Valley ERROR AMPLIFIER SECTION Input Bias Current VI Input Voltage Open Loop Gain GOPL SVR Supply Voltage Rejection Output Low Voltage VOL VOH Output High Voltage Output Source Current IO Output Sink Current Unit Gain Bandwidth Slew Rate SR PWM CURRENT SENSE SECTION Input Bias Current Ib IS Maximum Input Signal Delay to Output Gain Fault Threshold Voltage Vt SOFT START SECTION SS Charge Current ISSC ISSD SS Discharge Current SS Saturation Voltage VSSSAT VSSCLAMP SS Clamp Voltage LEADING EDGE BLANKING Internal Masking Time OUTPUT SECTION Output Low Voltage VOL Output High Voltage VOH VOUT CLAMP Output Clamp Voltage Collector Leakage
80 3.0 0.9 0.2 2.5 90 85 6 1.3 6 4 8 3 1.0 70 3 1.2 20 10 7 100
85 3.2 1.05 3.0 2.58
VFB to GND VCOMP = VFB VCOMP = 2 to 4V VCC = 12 to 20V Isink = 2mA Isource = 0.5mA, VFB = 2.3V VCOMP > 4V, VFB = 2.3V VCOMP = 1.1V, VFB = 2.7V
2.42 60
1.1 5 0.5 2 1.7 2.5
Isen = 0 VCOMP = 5V
0.92 2.85 1.1
15 1.08 100 3.15 1.3 26 15 0.6
Tj = 25C VSS = 0.6V Tj = 25C DC = 0%
14 5
IO = 250mA IO = 20mA; VCC = 12V IO = 200mA; VCC = 12V IO = 5mA; VCC = 20V VCC = 20V VC = 24V
20
(*) RT = RA//RB, RA = RB = 27k, see Fig. 23.
3/23
L5991 - L5991A
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter OUTPUT SECTION Fall Time Rise Time UVLO Saturation SUPPLY SECTION Startup voltage VCCON VCCOFF Vhys IS Iop Iq Minimum Operating Voltage UVLO Hysteresis Start Up Current Operating Current Quiescent Current Test Condition CO = 1nF CO = 2.5nF CO = 1nF CO = 2.5nF VCC = VC = 0 to VCCON; Isink = 10mA L5991 L5991A L5991 L5991A L5991 L5991A Before Turn-on at: VCC = VC = VCCON -0.5V CT = 1nF, RT = 13.3k, CO =1nF (After turn on), CT = 1nF, RT = 13.3k, CO =0nF I8 = 20mA IST-BY = 2mA Vcomp Falling Vcomp Rising Master Operation ISOURCE = 0.8mA Vclock = 3.5V Slave Operation Low Level High Level VSYNC = 3.5V 14 7.8 9 7 4.5 0.5 40 Min. Typ. 20 35 50 70 Max. 60 100 1.0 15 8.4 10 7.6 5 0.8 75 9 7.0 21 25 45 2.5 4.0 16 9 11 8.2 Unit ns ns ns ns V V V V V V V A mA mA V mV V V
120 13 10 30
VZ Zener Voltage STANDBY FUNCTION VREF-VST-BY Standby Threshold VT1 SYNCHRONIZATION SECTION V1 I1 V1 Clock Amplitude Clock Source Current Sync Pulse
4 3
7 1
V mA V V mA V V A A
Sync Pulse Current I1 OVER CURRENT PROTECTION Fault Threshold Voltage Vt DISABLE SECTION Shutdown threshold Input Bias Current Quiescent current After IqSH Disable
3.5 0.5 1.1 2.4 -1 1.2 2.5 330 1.3 2.6 1
Vpin14 = 0 to 3V VCC = 15V
Figure 1. L5991 - Quiescent current vs. input voltage. (X = 7.6V and Y= 8.4V for L5991A)
Iq [m A ] 30
Figure 2. L5991 - Quiescent current vs. input voltage (after disable). (X = 7.6V and Y= 8.4V for L5991A)
Iq [ A ] 350
20 8 6 4 0 .2 0 .1 5 0 .1 0 .0 5 0 0 4
V 1 4 = 0 , P in 2 = o p e n T j = 2 5 C
300 250 200 150 100 V 1 4 = V ref T j = 2 5 C
X Y
X
Y
50 0 0 4 8
8
12 16 V c c [V ]
20
24
28
12 16 V c c [V ]
20
24
4/23
L5991 - L5991A
Figure 3. Quiescent current vs. input voltage.
Iq [m A ] 9 .0 V 14 = 0, V 5 = V ref R t = 4.5Koh m ,T j = 25 C 8 .5 1 M hz 5 00K hz 3 00K hz 1 00K hz
Figure 4. Quiescent current vs. input voltage and switching frequency.
Iq [m A ] 36 30 24
1 M Hz
C o = 1 nF, T j = 25C D C = 0%
8 .0
18
5 00 K H z
12
7 .5
3 00 K H z 1 00 K H z
6 0
8 10 12 14 16 18 V c c [V ] 20 22 24
7 .0
8
10
12
14 16 V cc [V ]
18
20
22
Figure 5. Quiescent current vs. input voltage and switching frequency.
Iq [mA] 36
Co = 1nF, Tj = 25C
Figure 6. IC Consumption vs. Temperature.
[mA]
100
Operating current Vcc =15V, after turn-on RT=13.3k, CT=1nF DC=75%, Co=1nF Quiescent current Vcc =15V, after turn-on RT=13.3 k, CT=1nF DC = 0
30 24 18 12
DC = 100%
1MHz
10
500KHz
1
300KHz 100KHz
0.1
6 0 8 10 12 14 16 Vcc [V] 18 20 22
0.01 -50
Start-up current Vc=Vcc= Vccon-0.5V, before turn-on
-25
0
25
50
75
100
125
150
Junction temperature [C]
Figure 7. Reference voltage vs. load current.
Vref [V] 5.1
Figure 8. Vref vs. junction temperature.
Vref [V]) 5.1
5.05
Vcc=15V Tj = 25C
5.05
Vcc = 15V Iref = 1mA
5
5
4.95
4.95
4.9 0 5 10 Iref [mA] 15 20 25
4.9 -50
-25
0
25
50 Tj (C)
75
100
125
150
5/23
L5991 - L5991A
Figure 9. Vref vs. junction temperature.
Vref [V] 5.1
Vcc = 15V
Figure 10. Vref SVRR vs. switching frequency.
SVRR (dB)
120
Vcc=15V Vp-p=1V
5.05
Iref= 20mA
80 5
4.95
40
4.9 -50
-25
0
25
50 Tj (C)
75
100
125
150
0 1 10 100 1000 fsw (Hz) 10000
Figure 11. Output saturation.
Vsat = V
10
Figure 12. Output saturation.
V sat = V10 [V] 2.5
[V]
16
Vcc = Vc = 15V
14
Tj = 25C
2 1.5 1 0.5 0
Vc c = Vc = 15V T j = 25C
12
10
8
6 0 0.2 0.4 0.6 0.8 Isource [A] 1 1.2
0
0.2
0.4
0.6 Isink [A ]
0.8
1
1.2
Figure 13. UVLO Saturation
Ipin10 [mA] 50 40 30 20 10 Vcc < Vccon before turn-on
Figure 14. Timing resistor vs. switching frequency.
fsw (KHz) 5000
Vcc = 15V, V15 =0V
2000
Tj = 25C
1000 500
100pF
200
220pF
100
470pF
50 20
5.6nF 2.2nF 1nF
0
0
200
400
600 800 Vpin10 [mV]
1,000 1,200 1,400
10 10 20 Rt (kohm) 30 40
6/23
L5991 - L5991A
Figure 15. Switching frequency vs. temperature.
fsw (KHz) 320
Rt= 4.5Kohm, Ct = 1nF
Figure 16. Switching frequency vs. temperature.
fsw (KHz) 320
Rt= 4.5Kohm, Ct = 1nF
310
310
Vcc = 15V, V15=Vref
Vcc = 15V, V15= 0
300
300
290
290
280 -50
-25
0
25
50 Tj (C)
75
100
125
150
280 -50
-25
0
25
50 Tj (C)
75
100
125
150
Figure 17. Dead time vs Ct.
Dead time [ns]
Figure 18. Maximum Duty Cycle vs Vpin3.
DC Control Voltage Vpin3 [V] 3.5
V15 = Vref V15 = 0V
1,500 1,200
Rt =4.5Kohm V15 = 0V
3 2.5
900
V15 = Vref
2
Rt = 4.5Kohm,
600
1.5
300
Ct = 1nF
1
2 4 6 8 Timing capacitor Ct [nF] 10
0
10
20
30
40 50 60 70 Duty Cycle [%]
80
90 100
Figure 19. Delay to output vs junction temperature.
Delay to output (ns) 42
Figure 20. E/A frequency response.
G [dB] 150
Phase
140
40 38 36
120
100
100
80
34 32 30 28 -50 PIN10 = OPEN 1V pulse on PIN13
50
60
0
40
-25
0
25
50 Tj (C)
75
100
125
150
20
0.01
0.1
1
10 100 f (KHz)
1000
10000 100000
7/23
L5991 - L5991A
STANDBY FUNCTION The standby function, optimized for flyback topology, automatically detects a light load condition for the converter and decreases the oscillator frequency on that occurrence. The normal oscillation frequency is automatically resumed when the output load builds up and exceeds a defined threshold. This function allows to minimize power losses related to switching frequency, which represent the majority of losses in a lightly loaded flyback, without giving up the advantages of a higher switching frequency at heavy load. This is accomplished by monitoring the output of the Error Amplifier (VCOMP) that depends linearly on the peak primary current, except for an offset. If the the peak primary current decreases (as a result of a decrease of the power demanded by the load) and VCOMP falls below a fixed threshold (VT1), the oscillator frequency will be set to a lower value (fSB). When the peak primary current increases and VCOMP exceeds a second threshold (VT2) the oscillator frequency is set to the normal value (fosc). An appropriate hysteresis (VT2-VT1) prevents undesired frequency change when power is such that VCOMP moves close to the threshold. This operation is shown in fig. 21. Both the normal and the standby frequency are externally programmable. VT1 and VT2 are internally fixed but it is possible to adjust the thresholds in terms of input power level. APPLICATION INFORMATION Detailed Pin Function Description Pin 1. SYNC (In/Out Synchronization). This function allows the IC's oscillator either to synchronize other controllers (master) or to be synchronized to an external frequency (slave). As a master, the pin delivers positive pulses during the falling edge of the oscillator (see pin 2). In slave operation the circuit is edge triggered. Refer to fig. 23 to see how it works. When several IC work in parallel no master-slave designation is needed because the fastest one becomes autoFigure 22. Synchronizing the L5991.
RB SYNC 1 L5991 2 RCT CT 16 4 VREF RA ST-BY 1 L5991 2 RCT ROSC COSC SYNC L4981A (MASTER) 16 17 18 RCT CT ST-BY 16 L5991 (SLAVE) 4 1 2 RB VREF RA RCT 4 2 L5991 1 (MASTER) 16 ST-BY ROSC COSC RA VREF SYNC SYNC L4981A (SLAVE) 16 17 18
Figure 21. Standby dynamic operation.
Pin
fosc
Normal operation
PNO
fSB
PSB
1 2
VT1
Stand-by
3
VT2
4
VCOMP
matically the master. During the ramp-up of the oscillator the pin is pulled low by a 600A internal sink current generator. During the falling edge, that is when the pulse is released, the 600A pull-down is disconnected. The pin becomes a generator whose source capability is typically 7mA (with a voltage still higher than 3.5V). In fig. 22, some practical examples of synchronizing the L5991 are given. Since the device automatically diminishes its operating frequency under light load conditions, it is reasonable to suppose that synchronization will refer to normal operation and not to standby. Pin 2. RCT (Oscillator). Two resistors (RA and RB) and one capacitor (CT), connected as shown in fig. 23, allow to set separately the operating frequency of the oscillator in normal operation (fosc) and in standby mode (fSB). CT is charged from Vref through RA and RB in normal operation (STANDBY = HIGH), through RA only in standby ( STANDBY = LOW). See pin 16 description to see how the STANDBY signal is generated. When the voltage on CT reaches 3V, the capacitor is quickly internally discharged. As the voltage has dropped to 1V it starts being charged again.
SYNC
RB CT
(a)
(b)
D97IN728A
(c)
8/23
L5991 - L5991A
Figure 23. Oscillator and synchronization internal schematic.
SYNC VREF 4 1
R1 CLAMP RA RCT 2 D1 R3 R2 + 600A
D R
Q
CLK
RB CT ST-BY 16
50
STANDBY
D97IN729A
The oscillation frequency can be established with the aid of the diagrams of fig. 14, where RT will be intended as the parallel of RA and RB in normal operation and RT = RA in standby, or considering the following approximate relationships: fosc 1 CT (0.693 (RA // RB) + KT (1),
from fig. 14 or resulting from (1) and (2). To prevent the oscillator frequency from switching back and forth from fosc to fSB, the ratio fosc / fSB must not exceed 5.5. If during normal operation the IC is to be synchronized to an external oscillator, RA, RB and CT should be selected for a fosc lower than the master frequency in any condition (typically, 10-20% ), depending also on the tolerance of the parts. Pin 3. DC (Duty Cycle Control). By biasing this pin with a voltage between 1 and 3 V it is possible to set the maximum duty cycle between 0 and the upper extreme Dx (see pin 15). If Dmax is the desired maximum duty cycle, the voltage V3 to be applied to pin 3 is: V3 = 5 - 2(2-Dmax) (5) Dmax is determined by internal comparison between V3 and the oscillator ramp (see fig. 24), thus in case the device is synchronized to an external frequency fext (and therefore the oscillator amplitude is reduced), (5) changes into: Dmax V3 = 5 - 4 exp - (6) RT CT fext A voltage below 1V will inhibit the driver output stage. This could be used for a not-latched device disable, for example in case of overvoltage protection (see application ideas). If no limitation on the maximum duty cycle is required (i.e. DMAX = DX), the pin has to be left floating. An internal pull-up (see fig. 24) holds the voltage above 3V. Should the pin pick up noise (e.g.
9/23
which gives the normal operating frequency, and: 1 fSB CT (0.693 RA + KT) (2),
which gives the standby frequency, that is the one the converter will operate at when lightly loaded. In the above expressions, RA // RB means: RA RB RA//RB = , RA + RB while KT is defined as:
90 V15 = VREF (3), KT = 160 V15 = GND/OPEN
and is related to the duration of the falling-edge of the sawtooth: Td 30 10-9 + KT CT (4). Td is also the duration of the sync pulses delivered at pin 1 and defines the upper extreme of the duty cycle range, Dx (see pin 15 for DX definition and calculation) since the output is held low during the falling edge. In case V15 is connected to VREF, however, the switching frequency will be a half the values taken
L5991 - L5991A
during ESD tests), it can be connected to VREF through a 4.7k resistor. Figure 24. Duty cycle control. duce the oscillator frequency when the converter is lightly loaded (standby). Pin 7. SS (Soft-Start). At device start-up, a capacitor (Css) connected between this pin and SGND (pin 12) is charged by an internal current generator, ISSC, up to about 7V. During this ramp, the E/A output is clamped by the voltage across Css itself and allowed to rise linearly, starting from zero, up to the steady-state value imposed by the control loop. The maximum time interval during which the E/A is clamped, referred to as soft-start time, is approximately: 3 Rsense IQpk Css (7) ISSC where Rsense is the current sense resistor (see pin 13) and IQpk is the switch peak current (flowing through Rsense), which depends on the output load. Usually, CSS is selected for a TSS in the order of milliseconds. As mentioned before, the soft-start intervenes also in case of severe overload or short circuit on the output. Referring to fig. 25, pulse-by-pulse current limitation is somehow effective as long as Tss Figure 25. Regulation characteristic and related quantities.
VOUT D.C.M. C.C.M. A IQpk 1-2 *IQpk IQpk(max) B TON D TON(min)
D97IN495
VREF R1 DC
4
3A 3 23K
RA
R2
28K ST-BY
16 2
RB
RCT
+ -
TO PWM LOGIC
CT
D97IN727A
Pin 4. VREF (Reference Voltage). The device is provided with an accurate voltage reference (5V1.5%) able to deliver some mA to an external circuit. A small film capacitor (0.1 F typ.), connected between this pin and SGND, is recommended to ensure the stability of the generator and to prevent noise from affecting the reference. Before device turn-on, this pin has a sink current capability of 0.5mA. Pin 5. VFB (Error Amplifier Inverting Input). The feedback signal is applied to this pin and is compared to the E/A internal reference (2.5V). The E/A output generates the control voltage which fixes the duty cycle. The E/A features high gain-bandwidth product, which allows to broaden the bandwidth of the overall control loop, high slew-rate and current capability, which improves its large signal behavior. Usually the compensation network, which stabilizes the overall control loop, is connected between this pin and COMP (pin 6). Pin 6. COMP (Error Amplifier Output). Usually, this pin is used for frequency compensation and the relevant network is connected between this pin and VFB (pin 5). Compensation networks towards ground are not possible since the L5991 E/A is a voltage mode amplifier (low output impedance). See application ideas for some example of compensation techniques. It is worth mentioning that the calculation of the part values of the compensation network must take the standby frequency operation into account. In particular, this means that the open-loop crossover frequency must not exceed fSB/4 / fSB/5. The voltage on pin 6 is monitored in order to re10/23
C
ISHORT IOUT(max)
IOUT
the ON-time of the power switch can be reduced (from A to B). After the minimum ON-time is reached (from B onwards) the current is out of control. To prevent this risk, a comparator trips an overcurrent handling procedure, named 'hiccup' mode operation, when a voltage above 1.2V (point C) is detected on current sense input (ISEN, pin 13). Basically, the IC is turned off and then soft-started as long as the fault condition is detected. As a result, the operating point is moved abruptly to D, creating a foldback effect. Fig. 26 illustrates the operation. The oscillation frequency appearing on the softstart capacitor in case of permanent fault, referred to as 'hiccup" period, is approximately given by: Thic 4.5
1 ISSC
+
1 Css (8) ISSD
L5991 - L5991A
Since the system tries restarting each hiccup cycle, there is not any latchoff risk. "Hiccup" keeps the system in control in case of short circuits but does not eliminate power components overstress during pulse-by-pulse limitation (from A to C). Other external protection circuits are needed if a better control of overloads is required. Pin 8. VCC (Controller Supply). This pin supplies the signal part of the IC. The device is enabled as VCC voltage exceeds the start threshold and works as long as the voltage is above the UVLO threshold. Otherwise the device is shut down and the current consumption is extremely low (<150A). This is particularly useful for reducing the consumption of the start-up circuit (in the simplest case, just one resistor), which is one of the most significant contributions to power losses in standby. An internal Zener limits the voltage on VCC to 25V. The IC current consumption increases considerably if this limit is exceeded. A small film capacitor between this pin and SGND (pin 12), placed as close as possible to the IC, is recommended to filter high frequency noise. Pin 9. VC (Supply of the Power Stage). It supplies the driver of the external switch and therefore absorbs a pulsed current. Thus it is recommended to place a buffer capacitor (towards PGND, pin 11, as close as possible to the IC) able to sustain these current pulses and in order to avoid them inducing disturbances. This pin can be connected to the buffer capacitor directly or through a resistor, as shown in fig. 27, to control separately the turn-on and turn-off speed of the external switch, typically a PowerFigure 26. Hiccup mode operation.
IOUT SHORT
MOS. At turn-on the gate resistance is Rg + Rg', at turn-off is Rg only. Figure 27. Turn-on and turn-off speeds adjustment.
Rg'
VCC 8 13V DRIVE & CONTROL
VC 9
Rg(ON)=Rg+Rg' Rg(OFF)=Rg
10 OUT Rg
L5991
D97IN726
11 PGND
Pin 10. OUT (Driver Output). This pin is the output of the driver stage of the external power switch. Usually, this will be a PowerMOS, although the driver is powerful enough to drive BJT's (1.6A source, 2A sink, peak). The driver is made up of a totem pole with a highside NPN Darlington and a low-side VDMOS, thus there is no need of an external diode clamp to prevent voltage from going below ground. An internal clamp limits the voltage delivered to the gate at 13V. Thus it is possible to supply the driver (Pin 9) with higher voltages without any risk of damage for the gate oxide of the external MOS. The clamp does not cause any additional increase of power dissipation inside the chip since the current peak of the gate charge occurs when the gate voltage is few volts and the clamp is not active. Besides, no current flows when the gate voltage is 13V, steady state. Under UVLO conditions an internal circuit (shown
ISEN
FAULT
SS 5V 0.5V Thic
D98IN986
7V
time
11/23
L5991 - L5991A
in fig.28) holds the pin low in order to ensure that the external MOS cannot be turned on accidentally. The peculiarity of this circuit is its ability to mantain the same sink capability (typically, 20mA @ 1V) from VCC = 0V up to the start-up threshold. When the threshold is exceeded and the L5991 starts operating, VREFOK is pulled high (refer to fig. 28) and the circuit is disabled. It is then possible to omit the "bleeder" resistor (connected between the gate and the source of the MOS) ordinarily used to prevent undesired switching-on of the external MOS because of some leakage current. Figure 28. Pull-Down of the output in UVLO. Pin 13. ISEN (Current Sense). This pin is to be connected to the "hot" lead of the current sense resistor Rsense (being the other one grounded), to get a voltage ramp which is an image of the current of the switch (IQ). When this voltage is equal to: V13pk = IQpk Rsense = VCOMP - 1.4 (9) 3
10
OUT
the conduction of the switch is terminated. To increase the noise immunity, a "Leading Edge Blanking" of about 100ns is internally realized as shown in fig. 29. Because of that, the smoothing RC filter between this pin and Rsense could be removed or, at least, considerably reduced. Pin 14. DIS (Device Disable). When the voltage on pin 14 rises above 2.5V the IC is shut down and it is necessary to pull VCC (IC supply voltage, pin 8) below the UVLO threshold to allow the device to restart. The pin can be driven by an external logic signal in case of power management, as shown in fig. 30. It is also possible to realize an overvoltage protection, as shown in the section " Application Ideas".If used, bypass this pin to ground with a filter capacitor to avoid spurious activation due to noise spikes. If not, it must be connected to SGND. Pin 15. DC-LIM (Maximum Duty Cycle Limit). The upper extreme, Dx, of the duty cycle range depends on the voltage applied to this pin. Approximately, Dx RT (10) RT + 230
VREFOK
12
SGND
D97IN538
Pin 11. PGND (Power Ground). The current loop during the discharge of the gate of the external MOS is closed through this pin. This loop should be as short as possible to reduce EMI and run separately from signal currents return. Pin 12. SGND (Signal Ground). This ground references the control circuitry of the IC, so all the ground connections of the external parts related to control functions must lead to this pin. In laying out the PCB, care must be taken in preventing switched high currents from flowing through the SGND path.
if DC-LIM is grounded or left floating. Instead, Figure 29. Internal LEB.
I 3V 0 CLK ISEN 13 FROM E/A + 1.2V -
2V
+ -
+ -
PWM COMPARATOR
TO PWM LOGIC TO FAULT LOGIC
D97IN503
OVERCURRENT COMPARATOR
12/23
L5991 - L5991A
Figure 30. Disable (Latched). and the output switching frequency will be halved with respect to the oscillator one because an internal T flip-flop (see block diagram) is activated. Fig. 31 shows the operation. The half duty cycle option speeds up the discharge of the timing capacitor CT (in order to get duty cycles as close to 50% as possible) so the oscillator frequency - with the same timing components will be slightly higher. Pin 16. S-BY (Standby Function). The resistor RB, along with RA, sets the operating frequency of the oscillator in normal operation (fosc). In fact, as long as the STANDBY signal is high, the pin is internally connected to the reference voltage VREF by a N-channel FET (see fig. 32), so the timing capacitor CT is charged through RA and RB. When the STANDBY signal goes low the N-channel FET is turned off and the pin becomes floating. RB is
DISABLE SIGNAL
DIS
14
+ -
D R
Q
DISABLE
C 2.5V UVLO
D97IN502
connecting DC-LIM to VREF (half duty cycle option), Dx will be set approximately at: RT (11) 2 RT + 260 Figure 31. Half duty cycle option. Dx
td V15=GND V5=V13=GND
V2
DX =
tc tc + td
tc td V15=VREF V5=V13=GND
V10
V2 DX = V10
D97IN498
tc 2 *tc + td
tc
Figure 32. Standby function internal schematic and operation.
COMP 6 ISEN 13 2R R STANDBY VREF HIGH ST-BY 16 LOW RB 2 RCT RA VT1 2.5V VT2 4V VCOMP + R
DRIVER
OUT
2.5
2.5/4
STANDBY BLOCK
-
+
+
FB
5
-
LEVEL SHIFT
10V
4 STANDBY
CT
D97IN752B
13/23
L5991 - L5991A
now disconnected and CT is charged through RA only. In this way the oscillator frequency (fSB) will be lower. Refer to pin 2 description to see how to calculate the timing components. Typical values for VT1 and VT2 are 2.5 V and 4V respectively. This 1.5V hysteresis is enough to prevent undesired frequency change up to a 5.5 to 1 fosc/ fSB ratio. The value of VT1 is such that in a discontinuous flyback the standby frequency is activated when the input power is about 13% of the maximum. If necessary, it is possible to decrease the power threshold below 13% by adding a DC offset (Vo) on the current sense pin (13, ISEN). This will also allow a frequency change greater than 5.5 to 1. The following equations, useful for design, apply: PinSB = 0.367 - Vo 1 LP osc 2 Rsense 0.867 - Vo 1 LP SB 2 Rsense
2 2
(12),
2
PinNO =
(13),
osc 0.867 - Vo < SB 0.367 - Vo
(14),
where PinSB is the input power below which the L5991 recognizes a light load and switches the oscillator frequency from osc to fSB, PinNO is the input power above which the L5991 switches back from SB to osc and Lp the primary inductance of the flyback transformer. Connect to Vref or leave open this pin when stand-by function is not used.
Layout hints Generally speaking a proper circuitboard layout is vital for correct operation but is not an easy task. Careful component placing, correct traces routing, appropriate traces widths and, in case of high voltages, compliance with isolation distances are the major issues. The L5991 eases this task by putting two pins at disposal for separate current returns of bias (SGND) and switch drive currents (PGND) The matter is complex and only few important points will be here reminded. 1) All current returns (signal ground, power ground, shielding, etc.) should be routed separately and should be connected only at a single ground point. 2) Noise coupling can be reduced by minimizing the area circumscribed by current loops. This applies particularly to loops where high pulsed currents flow. 3) For high current paths, the traces should be doubled on the other side of the PCB whenever possible: this will reduce both the resistance and the inductance of the wiring. 4) Magnetic field radiation (and stray inductance) can be reduced by keeping all traces carrying switched currents as short as possible. 5) In general, traces carrying signal currents should run far from traces carrying pulsed currents or with quickly swinging voltages. From this viewpoint, particular care should be taken of the high impedance points (current sense input, feedback input, ...). It could be a good idea to route signal traces on one PCB side and power traces on the other side. 6) Provide adequate filtering of some crucial points of the circuit, such as voltage references, IC's supply pins, etc.
14/23
C11 4700pF 4KV C12
F01 AC 250V T3.15A BD01 R01 3.3 C02 0.1F C03 220F 400V R16 750K 17 D53 BYT11-600 C54 220F 100V C52 100F 250V C62 100F 100V 80V 10W GND 16 D05 1N4937 3 7 R07 47 R12 330K R13 47K R06 27 C04 47F 4 R08 22 2 R11 1K 13 C05 100pF R10 0.22 R54 1K 10 Q01 STP6 NA60FI 11 16 8 C56 470F 25V C57 470F 25V 14 9 8 13 12 D55 BYW100-100 +15V 5W C55 1000F 16V 15 14 D54 BYW100-100 6.3V 5W R18 47K 3W C10 10nF 100V R19 4.7M R20 4.7M 1 18 D52 BYT13-800 180V 65W
LF01
88 to 270 VAC
C01 0.1F
D06 1N4148 R17 750K R03 47K R04 47K D04 1N4148 C11 2.2nF
APPLICATION IDEAS Here follows a series of ideas/suggestions aimed at
C07 1F
C06
R5 12K
6800pF
10 D56 BYW100-100
-15V 5W R52 47
R9 24K
L5991
16 12 11 R21 100 5 C08 3.3nF 6 4N35
Figure 33. Typical application circuit for computer monitors (90W).
R53 4.7K
C58 47F 25V
7
C09 8.2nF
VR51 100K R55 300K C61 0.056F Q51 TL431 R58 4.7K
C59 0.01F R56 4.3K
VAC(V) Pin(W) Pout(W) 2 2.95 3.10 3.90 4.40
88
110
220
270
either improving performance or solving common application problems of L5991 based supplies.
L5991 - L5991A
D97IN730A
15/23
16/23
4700pF 4KV 4700pF 4KV BD01 2.2 BYW100-200 28V / 0.7A 100F 400V 10K BYW98-100 2 x 470F 16V GND 1.1M STK2N50 BAT46 BYW100-50 5V / 0.5A 22V 4.7K Naux N4 22 5.6K 33F/25V 15 22 10 STP4NA60 1K 13 470pF 12 11 7 5 470pF 3.9K 0.022F
110 0.93 0.55 1.14 1.57
D97IN618
F01 AC 250V T1A 4.7M 4.7M
L5991 - L5991A
LF01 C02 0.1F BZW06-154 N2 N1 1N4937 N3 2 x 330F 35V
85 TO C01 265 Vac 0.1F
1.1M
12V / 1.5A
BC337 33K
47K
470F 16V
100nF 4 3 2 16 14 98
22K
5.6K
3.3nF
L5991
0.47 1/2 W
Figure 34. Typical application circuit for inkjet printers (40W).
5.6K 1
220
1K
470 6 4N35
330nF
5.1K TL431 2.7K
270K
VAC(V)
85
220
265
Pin(W)
0.90
Pout(W)
L5991 - L5991A
Figure 35. Standby thresholds adjustment.
SGND
12 4
L5991
13
10
VREF RA
ISEN
R RSENSE
OPTIONAL
D97IN751A
Figure 36. Isolated MOSFET Drive & Current Transformer Sensing in 2-switch Topologies.
VIN VC 9 ISOLATION BOUNDARY
10
OUT
L5991
13 ISEN
12 PGND
11 SGND
D97IN761
Figure 37. Low consumption start-up.
VIN
2.2M
33K
STD1NB50-1 VCC 20V 47K VREF 4 8 L5991 11
T
SELF-SUPPLY WINDING
12
D97IN762B
Figure 38. Bipolar transistor driver.
VIN VCC 8 VC 9 10 OUT
13
ISEN
L5991
11 PGND
D97IN763
17/23
L5991 - L5991A
Figure 39. Typical E/A compensation networks.
+ 1.3mA Ri VFB Rd Cf Rf COMP 6 5 + EA 2R
From VO
2.5V
R
12 SGND
Error Amp compensation circuit for stabilizing any current-mode topology except for boost and flyback converters operating with continuous inductor current.
+ 1.3mA RP Ri CP Rd Cf VFB Rf COMP 6 5 + EA 2R
From VO
2.5V
R
12 SGND
D97IN507
Error Amp compensation circuit for stabilizing current-mode boost and flyback topologies operating with continuous inductor current.
Figure 40. Feedback with optocoupler.
VOUT
6
COMP
L5991
5 VFB
TL431
D97IN759
Figure 41. Slope compensation techniques.
ST-BY 16 4 RB VREF RA RCT 2 CT 2 CSLOPE
ST-BY VREF RB RA RCT RSLOPE CT ISEN RSENSE OPTIONAL
16 4 10
OUT R
I
L5991
13 12 SGND
I
RSLOPE
L5991
ISEN 13 12 SGND OPTIONAL
L5991
12 SGND OPTIONAL
D97IN760A
13
ISEN
RSLOPE
RSENSE
RSENSE
18/23
L5991 - L5991A
Figure 42. Protection against overvoltage/feedback disconnection (latched)
RSTART
RSTART
VCC DIS 8 14 12 SGND
VZ DIS
11 PGND
D97IN754
VCC 8 14 12 SGND
L5991
L5991
11 PGND
D98IN905
2.2K
Figure 43 Protection against overvoltage/feedback disconnection (not latched)
Figure 44. Device shutdown on overcurrent
2.5 RSENSE I R2 R1
RSTART
4
VREF R1
Ipk max
*
1-
Ipk
VREF
VCC 4 8
14
DIS R2 ISEN
L5991
DC
3 12
L5991
11
11
12 SGND
13
PGND
RSENSE OPTIONAL
D97IN755A
D97IN756A
Figure 45. Constant power in pulse-by-pulse current limitation (flyback discontinuous)
VIN 80 / 400VDC RFF OUT 10 RFF = 6*10
6
Lp
R*Lp RSENSE
L5991
11 PGND SGND 12 13
ISEN R RSENSE
D97IN757
Figure 46. Voltage mode operation.
DC 10K COMP 6 SGND
3
L5991
12 13 ISEN
D97IN758A
19/23
L5991 - L5991A
Figure 47. Device shutdown on mains undervoltage.
VIN 80/400VDC R1 VREF 4.7K
4
L5991
3 5.1 R2 10K SGND 12 PGND 11
D97IN750B
Figure 48. Synchronization to flyback pulses (for monitors).
SYNC 1K 5.1V
1
L5991
12 SGND
D97IN753A
20/23
L5991 - L5991A
DIM. MIN. a1 B b b1 D E e e3 F I L Z 0.51 0.77
mm TYP. MAX. MIN. 0.020 1.65 0.5 0.25 20 8.5 2.54 17.78 7.1 5.1 3.3 1.27 0.030
inch TYP. MAX.
OUTLINE AND MECHANICAL DATA
0.065 0.020 0.010 0.787 0.335 0.100 0.700 0.280 0.201 0.130
DIP16
0.050
21/23
L5991 - L5991A
mm MIN. A a1 a2 b b1 C c1 D (1) E e e3 F (1) G L M S 3.8 4.6 0.4 9.8 5.8 1.27 8.89 4 5.3 1.27 0.62 8(max.) 0.150 0.181 0.016 0.35 0.19 0.5 45 (typ.) 10 6.2 0.386 0.228 0.050 0.350 0.157 0.209 0.050 0.024 0.394 0.244 0.1 TYP. MAX. 1.75 0.25 1.6 0.46 0.25 0.014 0.007 0.020 0.004 MIN. inch TYP. MAX. 0.069 0.009 0.063 0.018 0.010
DIM.
OUTLINE AND MECHANICAL DATA
SO16 Narrow
(1) D and F do not include mold flash or protrusions. Mold flash or potrusions shall not exceed 0.15mm (.006inch).
22/23
L5991 - L5991A
Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specification mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2001 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com
23/23

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